Transmitters and receivers have long been used to communicate communication signals over a communication channel such as a unidirectional crosslink. The transmitter receives an analog input signal that is converted into digital form using a digital to analog converter providing a parallel output that is then converted into a serial data stream using a parallel to serial converter. The serial data bits stream is expanded to include frame synchronization words and forward error correction bits prior to transmission over the communications crosslink. The communicated signal is received by a receiver that performs forward error correction. The synchronization is achieved during removal of the frame synchronization words. The serial data stream is then converted into a parallel data stream using a serial to parallel converted. The parallel data stream can then be input into a digital to analog converter for providing the original analog input signal.
On the transmitter side of the communication channel, the analog signal has a baseband bandwidth of +/−f and is converted to n bit data words by the analog to digital converter at a sampling rate exceeding the Nyquist rate of 2f samples per second. These n bit data words are parallel data bit signals that are converted into a serial bit stream at a rate of 2fn bps. To determine the ordering of the least to most significant bits of the data words in the serial bit stream, unique and easily identifiable synchronization frame words are periodically inserted into the serial data stream. These synchronization frames words are overhead data and are typically one to ten percent of the informational data words. This overhead data increases the required rate of bits transmitted per second to (2fn(1+s/100)bps where s is the percentage of the serial bit stream associated with synchronization frame words. To accomplish the communications at the original data bit, the serial stream including the frame words and redundant error correction bits must be reclocked to a higher data rate having a shorter bit duration time. In order to maintain the data rate of the data words when the serial bit stream has additional synchronization frame words, the serial bit stream will be clocked at a higher rate. The received data stream must also therefore be coherently reclocked to recover the original data. Non-integer multiples of the transmitted data require frequency synthesizers and other digital word buffers.
Frame synchronization words are added to separate the groups of data words into frames of data words. Redundant error correction bits are also added at a particular code rate that relates the number of information data bits to the total number of communicated bits. Forward error correction redundant bits are added at a predetermined code rate to the data stream to correct for transmission errors. The forward error correction increases the actual data rate to 2fn(1+s/100)/r where r is the code rate. The data stream is then transmitted over the communication channel. Hence, the traditional approach to transmitting digitized signal information over a crosslink is to multiplex the parallel output of the analog to digital converter into an ordered serial data stream synchronized by added synchronization frame word and adding redundant error correction bits into the bit stream.
At the receiver side of the communication channel, the received incoming signal is processed in reverse order of the processing of the data on the transmit side. Forward error correction first corrects for transmission error while removing the redundant error correction bits. Frame synchronization is performed to determine the significance of the bits during which the frame synchronization words are removed from the data stream and the data is reclocked into a serial bit stream having a bit time duration equal to the bit time during of the serial data stream prior to frame synchronization in the transmitter. The serial data stream is then converted back into the original n bit parallel data words by sampling the serial data stream at the bit time duration and clocking the serial bit stream into a serial to parallel converter. The parallel data words for the serial to parallel converter are then input into a digital to analog converter for providing the original analog signal when an analog signal output is desirable.
It is desirable to eliminate the synchronization and forward error correction so as to reduce that total amount of data bits transmitted for improved channel communication efficiency. It also desirable to eliminate reclocking of the serial data streams in both transmitter and receiver reducing system complexity. One problem with conventional communications crosslink is the transmission of synchronization frame words and redundant error correction data bits. Another problem with conventional communications crosslinks is the power required for the additional hardware needed to reclock the data streams at higher data rate that further serves to decrease bandwidth efficiency.
The communication channel may be laser crosslink. The laser crosslink may not transmit analog signals directly with high power efficiency. Analog signals must be converted to digital samples and the bits transmitted must modulate the laser beam using digital modulation, for example, phase shift keying or on off keying. Small satellites, such as nanosatellites, are not able to generate much power because of the small solar power collection area. The use of laser crosslinks is desirable for transferring large amount of data to another satellite for data processing. Low power consumption components, and a reduction of the number of components are required to meet power limited resources. The reduction of the numbers of component is also desirable to increase reliability and reduce fabrication complexity. One problem with conventional crosslinks is the increased complexity for enabling frame synchronization and forward error correction. Another problem with laser crosslinks transmitting data streams is required additional components for reclocking that complicate the crosslink design as well as dissipating more power from the already power limited resources.
Referring to FIGS. 1A and 1B, first and second order modulators have been used to modulate an analog input signal 10 into a modulated output 12. The output 12 is a binary output. In the first order sigma delta modulator of FIG. 1A, the input signal is fed into a summer 14 providing an input error signal that is fed into an integrated 16. The input error signal from the summer 14 is integrated by the integrator 16 to form an accumulated error signal that becomes an input to a one bit quantizer 18. The output of the one bit quantizer 18 is the binary output 12 and is the sign of accumulated error signal. The output of the quantizer 18 is fed into the DAC 20 providing a converted error equal to a gain amplifier 22. A gain amplifier 22 provides gain G of the converted error signal from output of the DAC 20 to provide an amplified error signal to the summer 14. The amplified error signal output of the gain amplifier 22 is fed back into the summer 14 to be subtracted from the analog input signal 10 to provide an input error signal. Hence, the first order modulator comprises a first order feedback loop. The first order feedback loop forces the average of the converted error signal output of the DAC 20 to be equal to the analog input signal 10 plus an error signal. The output of the first order modulator 12 is a series of +1 or −1 pulses of varying duration. The second order modulator of FIG. 1B, comprises a first order feedback loop and a second order feedback loop. The second order feedback loop comprises a summer 14a, integrator 16a, the one bit quantizer 18, a DAC 20a, and a gain amplifier 22a, whereas the first order feedback loop comprises a summer 14b, integrator 16b, the one bit quantizer 18, a DAC 20b, and a gain amplifier 22b. The first order feedback loop serves to generate a first order input error signal at summer 14b, while the second order feedback loop serves to generate a second order input error signal of first order input error signal. The presence of a second order feedback loop reduces the magnitude of the overall error at the binary output 12. The binary output 12 of the sigma delta modulator is a series of pulses of +1 or −1 of varying duration. Hence, the sigma delta modulators convert the analog input 10 into the binary output 12. The sigma delta modulators have been used as modulators for digital communications, and as part of an analog to digital converter. These sigma delta modulators have been used in analog to digital converters comprising a sigma delta modulator and a digital filter. These sigma delta modulators have also been used as opposing modulators and demodulators in communication links for communicating an analog signal by transmitting a binary communication signal through the crosslink. In the sigma delta analog-to-digital converter, the sigma delta modulator and digital interpolating filter are an integrated package. While sigma delta modulators offer analog signal modulation, these modulators have not been used for laser crosslink communication where digital signal samples rather than analog samples are desired. These and other disadvantages are solved or reduced using the invention.